A Study on the Impact of Nano-Scale TSVs on 3D IC Designs
نویسندگان
چکیده
One of the most effective ways to minimize the area and capacitance overhead caused by through-silicon vias (TSVs) in 3D ICs is to reduce the size of TSVs themselves. Today, the diameter of the smallest TSV available is around 1μm, and it is expected to reach sub-micron dimensions in a few years. This downscaling of TSVs requires research on the impact of nanoscale TSVs on the quality of 3D IC designs to provide academia and industry with the quantified effects. In this paper, we investigate the impact of nano-scale TSVs on the area, wirelength, and delay quality of today and future 3D IC designs. For our future process technology, we develop a 22nm process library. We also use four sets of TSV-related dimensions for today and future TSVs. Based on these resources, we present a thorough study on the impact of nano-scale TSVs on the design quality of today and future 3D ICs.
منابع مشابه
13th Int'l Symposium on Quality Electronic Design
Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller footprint area, shorter wirelength, and better performance than 2D ICs. However, the quality of 3D ICs is strongly dependent on TSV dimensions and parasitics. Using large TSVs may cause silicon area overhead and reduce the amount of wirelength reduction in 3D ICs. In addition, non-negligible TSV p...
متن کاملTSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs
This article presents several grand challenges in the area of physical design for through-silicon via (TSV) based 3D ICs. Most of these issues are centered around TSVs, which are a new element of the 3D IC layout. Fundamental understanding of the electrical, mechanical, and thermal properties of TSVs is essential in successful physical design of TSV-based 3D ICs. Further investigation of the im...
متن کاملReliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling
A robust physical design of 3D-IC requires investigation on through-silicon-via (TSV). The large temperature and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model...
متن کاملRF Modeling of Through Silicon Vias (TSVs) in 3D IC
1. Introduction As the size of transistor keeps shrinking, advance of CMOS technology becomes more difficult and will eventually reach the physical limitation. To continuously reduce the form factor of the system with multiple chips, one straight forward solution is using stacked dies, called three-dimensional integrated circuits (3D IC). Recently, the technology of Through Silicon Vias (TSVs),...
متن کامل3D IC and Through-Silicon-Via (TSV) Reliability
this report shows the survey of reliability of 3D IC manufactory and its robustness. Firstly, we consider the reliability of the manufactory of 3D IC. The process-induced thermal stresses around TSVs raise serious reliability issues such as Si cracking and performance degradation of devices. Finite element analysis (FEA) combined with analytical methods is introduced to investigate this issue, ...
متن کامل